There is a continued effort to further develop, refine and improve the performance of semiconductor circuits. Speed, power, cost, circuit density and other such items are factors on which emphasis is placed to improve the performance of such circuits. Circuit biasing is another consideration which affects certain of the noted factors.
Developers of early semiconductor circuits recognized that biasing of the various chip elements had an affect on the performance of the circuits. The DC voltage supply and ground connections were, of course, necessary to provide the chip with electrical power. In addition, it was recognized that by applying a separate bias voltage to the chip substrate, the operation of MOS transistor performance could be affected. Particularly, by properly biasing the substrate of N-channel (NMOS) circuits, the speed thereof could be improved. Thus, in addition to providing supply voltage and ground terminals to an integrated circuit chip, a separate bias voltage terminal was also provided. While the circuit performance improved in response to the proper bias voltage, a separate bias supply was required and printed wire board connections were necessary to route the bias voltage to each integrated circuit.
The importance of the proper substrate biasing of N-channel or CMOS memories has become a significant concern in sophisticated semiconductor circuits requiring optimum performance. For example, in high density, high speed memories, such as CMOS memories having upwardly of 4 million storage locations, optimum performance of each storage cell can be realized only by properly biasing the substrate. In addition to improved speed performance, with proper substrate biasing the bit line capacitance and minority carrier injection can also be reduced, thereby facilitating the storage capabilities of each cell. Also, with reduced minority carriers in the substrate, the possibility of CMOS circuit latchup is further reduced.
Substrate bias generators have been integrated with other circuits on semiconductor chips to thereby eliminate the need for external power supplies and the extra bias voltage terminal. One type of on-chip bias generator is disclosed in the technical article "An On-Chip Back-Bias Generator For MOS Dynamic Memory", IEEE Journal of Solid State Circuits, Vol. SC-15, No. 5, October, 1980. With such an on-chip generator, single supply integrated circuits chips are made possible. Generally, the external power requirements of most integrated circuit chips comprise +5 volts (V.sub.cc) and ground (V.sub.ss). An internal generated voltage of about negative 2-3 volts (V.sub.bb) is utilized for biasing the substrate. The bias generators themselves comprise an oscillator and a charge pump for deriving the negative bias voltage from the positive supply voltage. Typically, the voltage relationship can be expressed as: EQU V.sub.bb =-0.5V.sub.cc
As can be seen, if the supply voltage V.sub.cc changes, the substrate bias V.sub.bb also changes. One concern which is typical of the majority of charge pumps is that if the supply voltage V.sub.cc increases, the bias voltage V.sub.bb also increases, albeit in the negative direction. Hence, the voltage difference therebetween becomes greater and thus exposes various circuit junctions to an increased electric field, and to the possibility of a junction breakdown. The bias generator disclosed in the noted article also makes provisions for regulating the bias voltage V.sub.bb to thereby make it independent of changes in the supply voltage V.sub.cc. For high performance circuit operation and for purposes of reliability, it is desirable to regulate the bias voltage to a higher degree.
It can be seen from the foregoing that a need exists for an improved substrate bias voltage regulator which further improves regulation to further optimize circuit reliability and performance. There is an associated need for a bias voltage regulator for controlling the bias voltage V.sub.bb so as to render it independent of not only supply voltage changes, but also of changes in chip temperature and process variables occurring during circuit fabrication.